These AMD Mobile processors will be supported by the ALi MAGiK1 M1647 and the VIA Apollo KT133A. The MAGiK1 M1647 chipset includes a dual-memory controller capable of supporting both SDRAM and DDR RAM and supports AGP 4X through an external video controller. The VIA KT133A supports only SDRAM and also offers dedicated AGP 4X video.

The Southbridge of both chipsets includes various integrated functions such as sound, modem and AMD PowerNow! support, although the M1535+ mobile Southbridge of the ALi chipset seems a bit more targeted to specific notebook use. There are currently no integrated/UMA video chipsets that support the new Mobile Athlon 4 or Duron, although these may be announced in the very near future.

Although some performance fans may hope that the Palomino and Morgan cores signify an AMD transition to the 0.13 micron die size, you may have to wait until next year for that. The Palomino and Morgan cores are still manufactured using the 0.18 micron process but both now use the copper interconnect process out of Fab 30 in Dresden. This is the same process used with the newest, high-speed Athlon processors and this manufacturing process would certainly allow lower voltages at lower core speeds, as well as offering the potential of decreased core heat generation.

The benefits of the enhanced Palomino and Morgan designs run a bit deeper than simply enhanced core production and lower voltages. These new AMD designs also incorporate PowerNow! functionality and an on-die temperature diode into the CPU, add a hardware data pre-fetch, and enhance the current 3DNow! Technology with additional SSE instructions into the new 3DNow! Professional.

The data pre-fetch aspect of the new AMD Palomino and Morgan cores enables the processor to gather data from system memory, well before the processor needs it. A capable pre-fetch design can speed up CPU processing, reduce memory latencies through hardware and help to provide greater overall system performance.

This is interesting technology because it already exists in both 3DNow! and SSE optimized applications, where the software itself would aid in data pre-fetching. The new AMD design creates a more hardware-based solution and offers greater performance even using non-optimized software. How truly effective AMD's data pre-fetch is will depend largely on the application and exactly how data intensive it is. One interesting point is that the data pre-fetch seems to be better suited to DDR RAM system than those with SDRAM, as the lower memory latencies yield greater potential returns on a system with higher memory bandwidth.

Another minor enhancement concerns the processor's Translation Look-aside Buffer (or TLB) which provides space and structure for data and instruction address translation. The changes here essentially expand the L1 entries, design exclusivity into the L2 TLB architecture and allow for speculative reloads. If this sounds a bit technical, it really means that the newer Palomino and Morgan cores have more a greater number of translation buffers (good), have changed the L2 buffers to not share register space (good) and can take a calculated risk on reloading data (potentially good).