The TM5400 is intended for lightweight and full-featured mobile PC's running Windows operating systems. It can run from 500MHz to 700MHz and resides on a 73mm^2 die. It features 64KB of L1 instruction cache, 64KB of L1 data cache and 256K of on-chip L2 cache. It supports 66MHz to 133MHz SDRAM as well as 100MHz to 166MHz DDR SDRAM. The TM5400 is currently sampling and will go into production in Mid-2000.

The Crusoe is fabricated and packaged by IBM's Microelectronic Division on a .22 micron process. Both chips have an integrated northbridge, which is usually a separate part. The integrated northbridge supplies the PCI interface, the memory controller, and a serial I/O port for reading software from ROM (more on the ROM later).

Both versions of the Crusoe take up very little silicon and are therefore relatively cheap to produce. The market of the TM3120 doesn't need an L2 cache since it's not a speed-oriented market. The market of the TM5400 is very speed conscious and the large on-chip L1 and L2 cache will help keep the speed acceptable.

TM5400                                     TM3120