Both SRAM and DRAM consist of one or more rectangular arrays of memory cells, and include circuitry to decode addresses and implement the read and write operations. There may also be circuitry to implement burst operations and other special features. The number of arrays used depends upon the size and speed of the memory, as well as the number of I/O lines.

The memory arrays are organized into rows (wordlines) and columns (bitlines) of memory cells. Each cell represents a single bit, and has a unique address that is defined by the intersection of a row and column. In a cache SRAM chip, each cell is typically associated with a particular input/output pin while the DRAM cells are connected to a set of transistors called 'sense amplifiers'. These sense amps hold and amplify the charge that is read from or is to be written to the cell, and are connected to the input/output pins.

An SRAM cell is basically a 'flip-flop', which may be in one of two states (interpreted as 0 or 1). These cells are typically made from 6 transistors, and will retain their current state until it is changed or the power is removed. Other circuitry in the chip includes address logic (for selecting rows and columns), read logic (for taking data from the cell and putting it on the outputs) and write logic (for taking data from the input and placing it in the cells). There may also be circuits for implementing special features, such as pipelining, burst addresses and synchronous operation.

A DRAM cell is a capacitor that is charged to be either a 0 or 1, and which needs to be refreshed frequently, as 'leakage' causes the charge to bleed off. Due to the high capacitance, the speed of getting data out of a DRAM cell is slower than from an SRAM cell. Other circuitry includes sense amplifiers (transistors that amplify the charge read from a cell), address logic, Row Address and Column Address Select logic (for the /RAS and /CAS signals which initiate and terminate read and write operations), read logic and write logic. There will also be circuitry for handling refresh operations and special features.