As with previous Duron releases, the 950 MHz model is simply a core speed increase using the existing technology. This means that the line jumps another 50 MHz up to the Duron 950 and features the standard 128KB L1/64KB L2 cache, .18 micron core, 1.6V core voltage and 200 MHz DDR system bus. The Duron 950 is also a continuation of the AMD aluminum interconnect process, and we won't be seeing any copper interconnects until at least the Morgan debut.

While the Duron 950 does not herald the introduction of any new technology, it is good news for system vendors and upgraders alike. The new Duron is fully supported using current motherboard technology, and is a snap to integrate into existing PC designs or to use as a possible upgrade for one of the initial Duron models.

The Duron features a cache format of 128k of L1 cache and 64K of full-speed, on-die L2 cache, and helps AMD differentiate the Duron from its Athlon counterpart. This compares to the 32K L1/128K L2 cache included with the Intel Celeron and the 32K L1/256K L2 cache of the Pentium III. The Duron design is actually quite innovative, given that it matches the Athlon in L1 cache size, but has a drastically reduced L2.

Looking a bit deeper, we find that AMD uses a slightly different cache design than Intel. The 192K total cache of the Duron may not seem to have a large size advantage over the 160K total of the Celeron, but AMD uses an exclusive cache design. This means that at any given time, the 192K is available to the processor. With the Intel design, data can be duplicated in both the L1 and L2 cache, which translates into only a total of 128K of actual cache memory. AMD's Duron also uses a highly efficient 16-way set-associative L2 cache, while the Celeron has only a 4-way set-associative L2 cache.

Of course Intel also has a few aces up their sleeve, and the Celeron and Pentium III processor cache have lower latencies and a much wider 256-bit data bus. With the Duron having higher cache latencies and only a 64-bit data bus, you can see there are inherent benefits to both cache architectures.