While Intel officially describes the Coppermine design as a refresh or tune-up to the already strong Pentium III design, the truth is they've put a good deal of technology and improvements into the design that will carry the majority of the business for the next calendar year.
Beginning with a die-shrink from .25um to .18um, and the addition of 256KB of on-die L2 cache, the Coppermine CPU is a departure from Intel's traditional model of off-die L2 cache modules.
Here's a look at the detailed specification sheet on the new design, with explanations regarding the new featureset:
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Intel Coppermine Core
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Pentium III Processor Core
256KB Advanced Transfer Cache On-Die (ATC)
- 8-way set associative, 1024 sets
- 32 byte line (32 bytes data, 4 bytes ECC) every 2 clocks,
equals 11.7GB/sec throughput at 733MHz
- 36-bit physical address space
- 4 x reduction in latency versus Katmai P3 L2
- Cache bus speed fully scalable with core frequency
- 288-bit transfer width (256 data, 32 ECC)
- 2 cycle back to back throughput
Advanced System Buffering (ASB)
- 6 Fill Buffers (increased from 4) offer increase of 50% in
concurrent non-blocking data cache operations.
- 8 Bus Queue Entries (increased from 4) allow more
outstanding memory/bus operations.
- 4 Writeback Buffers (increased from 1) offer reduced
blocking during cache replacement operations along with
faster deallocation time for fill buffers.
.18um Manufacturing Process
- Decrease in minimum gate dimension for improved transistor
speed.
- Fluorine-doped SiO2 (SiOF) dielectric for reduced
capacitance resulting in global speed increase.
6 Metal Layer Process
- Additional metal layer for routing density enables full-speed
integrated L2 interface.
28 Million Transistors
106mm2 Die Size
1.1v - 1.7v Operation
On-Die GTL+ Termination
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