Advanced Transfer Cache Performance Benefits
Bandwidth (256-bit data, 2 clock back-to-back throughput)
- 32 Bytes every 2 clocks (11.2GByte/s @700MHz)
- Scaleable with core frequency
- Enables full system bus utilization
Latency ( > 4x improvement in L2 latency)
- Decreases penalty of L1 cache misses
- Reduces snoop stalls >20x compared to today's Pentium® III Xeon™ processor
Associativity (8-way set associative, 1024 sets)
- Increases performance of cache for real applications
- ~3% benefit for integer, business and workstation workloads
- ~6% benefit for server oriented workloads( TPC-C)
Advanced System Buffering
- Balanced increase in buffers to minimize bottlenecks
- Buffer sizes maximize utilization of the 133MHz system bus bandwidth
- 6 Fill buffers (increased from 4)
- 50% increase in concurrent non-blocking data cache operations
- 8 Bus queue entries (increased from 4)
- Allows more outstanding memory/bus operations
- 4 Writeback buffers (increased from 1)
- Reduced blocking during cache replacement operations
- Faster deallocation time for fill buffers
The Pentium 3 500E and 550E Coppermine CPUs are designed using the "Flip Chip-Pin Grid Array" package, or FC-PGA for short. It's an interesting shift from previous Intel CPUs, in that the chip die is actually "flipped" upside down onto the S370 pin package so that the chip core faces upwards. This direct link to the pins eliminates any possible cavity inside the chip and also ensures there are no bond wires. The biggest plus to the FC-PGA format is its exceptional heat dissipation. With the Coppermine FC-PGA's silicon core exposed upwards, the CPU cooler can be attached directly to the back of the chip die. Moving to the FC-PGA format allows the CPU core to face away from the motherboard's CPU socket, further eliminating any potential heat buildup.
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